Le_principale Project Status
Project File: gene_pseudo_20_03_2014__2.xise Parser Errors: No Errors
Module Name: Le_principale Implementation State: Programming File Generated
Target Device: xc3s200-5ft256
  • Errors:
No Errors
Product Version:ISE 14.6
  • Warnings:
10 Warnings (10 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 17 3,840 1%  
Number of 4 input LUTs 1 3,840 1%  
Number of occupied Slices 17 1,920 1%  
    Number of Slices containing only related logic 17 17 100%  
    Number of Slices containing unrelated logic 0 17 0%  
Total Number of 4 input LUTs 1 3,840 1%  
Number of bonded IOBs 10 173 5%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 2.56      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentlun. 31. mars 17:01:06 2014001 Info (0 new)
Translation ReportCurrentlun. 31. mars 17:01:12 2014000
Map ReportCurrentlun. 31. mars 17:01:16 2014002 Infos (0 new)
Place and Route ReportCurrentlun. 31. mars 17:01:21 2014010 Warnings (10 new)2 Infos (1 new)
Power Report     
Post-PAR Static Timing ReportCurrentlun. 31. mars 17:01:25 2014006 Infos (0 new)
Bitgen ReportCurrentlun. 31. mars 17:01:29 2014001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentlun. 31. mars 17:01:29 2014
WebTalk Log FileCurrentlun. 31. mars 17:01:30 2014

Date Generated: 04/10/2014 - 09:16:02