Le_principale Project Status
Project File: gene_pseudo_20_03_2014__2.xise Parser Errors: No Errors
Module Name: Le_principale Implementation State: Programming File Generated
Target Device: xc3s200-5ft256
  • Errors:
No Errors
Product Version:ISE 14.6
  • Warnings:
10 Warnings (7 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 10 3,840 1%  
Number of 4 input LUTs 1 3,840 1%  
Number of occupied Slices 10 1,920 1%  
    Number of Slices containing only related logic 10 10 100%  
    Number of Slices containing unrelated logic 0 10 0%  
Total Number of 4 input LUTs 1 3,840 1%  
Number of bonded IOBs 3 173 1%  
Number of BUFGMUXs 1 8 12%  
Average Fanout of Non-Clock Nets 2.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentmer. 26. mars 17:33:29 201407 Warnings (7 new)2 Infos (0 new)
Translation ReportCurrentmer. 26. mars 17:33:35 2014000
Map ReportCurrentmer. 26. mars 17:33:40 2014002 Infos (0 new)
Place and Route ReportCurrentmer. 26. mars 17:33:45 201403 Warnings (0 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentmer. 26. mars 17:33:49 2014006 Infos (0 new)
Bitgen ReportCurrentmer. 26. mars 17:33:53 2014001 Info (0 new)
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentmer. 26. mars 17:33:53 2014
WebTalk Log FileCurrentmer. 26. mars 17:33:59 2014

Date Generated: 04/13/2014 - 17:09:40