Altium

Design Rule Verification Report

Date: 15/03/2017
Time: 16:05:14
Elapsed Time: 00:00:01
Filename: C:\Users\Public\Documents\Altium\Projects\PCB_Optali\Proto.PcbDoc
Warnings: 0
Rule Violations: 8

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=8mil) (All),(All) 6
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=6mil) (Max=8mil) (Preferred=8mil) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All) 0
Hole Size Constraint (Min=1mil) (Max=100mil) (All) 0
Hole To Hole Clearance (Gap=10mil) (All),(All) 0
Minimum Solder Mask Sliver (Gap=10mil) (All),(All) 0
Silk To Solder Mask (Clearance=10mil) (IsPad),(All) 1
Silk to Silk (Clearance=10mil) (All),(All) 1
Net Antennae (Tolerance=0mil) (All) 0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All) 0
Total 8

Clearance Constraint (Gap=8mil) (All),(All)
Clearance Constraint: (7.874mil < 8mil) Between Pad A1-2(2535mil,3399.252mil) on Top Layer And Pad A1-1(2535mil,3415mil) on Top Layer
Clearance Constraint: (7.874mil < 8mil) Between Pad A1-3(2535mil,3383.504mil) on Top Layer And Pad A1-2(2535mil,3399.252mil) on Top Layer
Clearance Constraint: (7.874mil < 8mil) Between Pad A1-4(2535mil,3367.756mil) on Top Layer And Pad A1-3(2535mil,3383.504mil) on Top Layer
Clearance Constraint: (7.874mil < 8mil) Between Pad A1-9(2610.984mil,3399.252mil) on Top Layer And Pad A1-10(2610.984mil,3415mil) on Top Layer
Clearance Constraint: (7.874mil < 8mil) Between Pad A1-8(2610.984mil,3383.504mil) on Top Layer And Pad A1-9(2610.984mil,3399.252mil) on Top Layer
Clearance Constraint: (7.874mil < 8mil) Between Pad A1-7(2610.984mil,3367.756mil) on Top Layer And Pad A1-8(2610.984mil,3383.504mil) on Top Layer
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Silk To Solder Mask (Clearance=10mil) (IsPad),(All)
Silk To Solder Mask Clearance Constraint: (7.874mil < 10mil) Between Arc (2507.948mil,3427.289mil) on Top Overlay And Pad A1-1(2535mil,3415mil) on Top Layer [Top Overlay] to [Top Solder] clearance [7.874mil]
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Silk to Silk (Clearance=10mil) (All),(All)
Silk To Silk Clearance Constraint: (6.691mil < 10mil) Between Text "Res5" (2605mil,3487.441mil) on Top Overlay And Text "Res4" (2705mil,3495mil) on Top Overlay Silk Text to Silk Clearance [6.691mil]
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